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—New six-layer planarized process increases the integration level of superconducting ICs and critical current density of Josephson junctions in high-end computing, advanced wireless communications and instrumentation—
Elmsford, New York (July 05, 2013)—HYPRES, Inc., the Digital Superconductor Company™, announces the commercial availability of its newest six-layer planarized chip fabrication process. This new process increases the integration level of superconducting ICs and critical current density of Josephson junctions, making it ideal for customers developing high performance, energy efficient solutions for high-end computing, advanced wireless communications and instrumentation.
“This is an exciting milestone for HYPRES, its customers, and the superconductor electronics community,” said Oleg Mukhanov, Ph.D., Chief Technology Officer at HYPRES. “Next generation superconductor circuit development requires commercially available fabrication processes well beyond today’s four metal layers and critical current densities. We have made six planarized layers—and soon, more—and various increased critical current densities available as part of our commercial foundry services. We made our first customer delivery earlier this year and have new orders in process.”
HYPRES is well known in the industry as a complete digital superconductor electronics company, offering design development, simulation, layout, fabrication, high speed testing and packaging in a world-class production environment. It is the premier commercial manufacturer of superconductor ICs used in Primary Voltage Standard Systems and many other applications around the world. Today, digital superconductor devices are being demonstrated for specific applications where unparalleled performance advantages make them a compelling alternative to other chip designs. These applications include digital circuits for energy efficient high-end computing (exascale and beyond), analog and mixed signal circuits for advanced wireless communications, and mission critical instrumentation.
The six-layer fabrication process, developed over several years, features many new processes and techniques included in provisional patent application Rapid Integrated Planarized Process for Layer Extension (RIPPLE). This new optimized process was offered to customers after the completion and thorough evaluation of several internal design iterations and successful production of working circuits. Earlier this year, Stanford University became the first commercial customer of the new fabrication process. Today, HYPRES is processing a second order from Stanford based on the university’s new design parameters and specific needs.
“Our new fabrication process is rapid—approximately 20 percent faster per layer—and is easily integrated with our current device designs by adding two new layers under the ground plane,” explained Daniel Yohannes, Ph.D., Director of Fabrication Operations at HYPRES. “It is performed with one chemical mechanical polishing planarization step per layer. Moreover, the process is extensible beyond the current six layers, paving the way for a soon-to-be-announced five-year, multi-layer roadmap the company will pursue.”
Dr. Yohannes explained that the new process is implemented on its Canon 5X reduction stepper capable of supporting 250 nm resolution limits. The new stepper process is very versatile and can be quickly tailored toward specific customer needs. “Special Runs” allow customers to order chips at their convenience, rather than timing orders to one of the foundry’s regular mask schedules. In addition, the new process provides customers with increased purchasing value.
HYPRES’ new fabrication process is open and available for broad commercial use. For more information on the new process, the design tools, or to order chips, please visit http://www.hypres.com/foundry or email email@example.com