Schedule & Updates

Mask Release Schedule

Date Current Density (kA/cm2); Process Grade
Feb. 24, 2016 10; 4.5 (4- & 6-layer) C
March 8, 2016 0.1; 4.5; dual (0.1&4.5) (4-layer) C&E
April 4, 2016 0.1; 4.5 (4-layer & HKI) C
May 9, 2016 4.5; 10 (4-&6-layer) C
June 6, 2016 20; 70; 100 (4-layer) E
July 27, 2016 4.5; 10 (4 layer & HKI) C
July 27, 2016 4.5; 10 (4- & 6-layer) C
August 15, 2016 0.1; 4.5 dual (0.1&4.5); (4-layer) C&E
Sept. 19, 2016 20; 70; 100 (4-layer) E
Nov. 7, 2016 10; 4.5 (4-layer & HKI) C
Nov. 7, 2016 10; 4.5 (4- &6- layer) C
 C=Commercial;        E=Experimental (Best Effort)  HKI=High Kinetic Inductance

Release dates and current densities for each run are tentative and are subject to change. Please check this page periodically for updates.

Standard Niobium Circuit Foundry–UPDATES

(Important; please read)

08/02/2011 - Please note that we support only cell placements that are at 0 or 90 degrees. Other orientations will “snap” to the nearest 0 or 90 degree.

01/05/2010 — You must reserve your chip sites at least two weeks prior to the release date.

04/14/2009 – Four rectangles, each 300um x 300um, at the four corners of every chip is reserved for labeling. Please do not put any active circuits in these four locations.

02/09/2009 – New pricing went into effect in February 2009 for foundry chips. Please consult HYPRES and obtain an updated quote before submitting layouts.

10/28/2008 – If you get permission to update an already-submitted layout, submit the revised layout without changing the names of the parent chips and/or the name of the main cell containing the parent chips. 5mm x 5mm or 10mm x 10mm chips are considered parent chips.

07/11/2008 – Please note that the minimum linewidths specified in the design rules are after-fabrication minimum linewidths. You need to account for biases in your layouts to avoid having linewidths less than the minimum allowed.

12/14/2007 – (for your information only; for most, no layout implications) — We routinely bias up junction and resistor mask layers (2, 4, and 9) by 0.1um. The biases for these layers exhibited in the table in the section 3.1 of the design rules are with respect to the layouts and not the mask layers.

04/24/07 – When placing chips in a master cell, center the first chip at (0, 0) and place the rest of your chips in the same master file. The center to center chip spacing should be 5.150 mm in X and/or Y directions in the master file. Do not flatten your chips. Each 5mm x 5mm chip in the master cell should be a top level cell without any structures defined in it. In other words, each chip in the master cell should only be defined by its boundaries. If you need an example please send a request to or down load them here:

  • Layout of a junction defined using anodization.
  • Layout for a simple logic circuit.
  • Layout of a master cell.

08/03/06 – There are major changes in the design rules. Please read the rules before submitting designs. For example, new layers have been added to the process, which should be included in the designs beginning August 2006.

10/27/05 – If you use logos or structures in your layouts that are not part of active circuits, make sure that they also follow design rules. We will reject layouts that contain excessive design rule violations.

9/8/05 – When submitting layouts, please follow these rules (more details are in the design rules):

  • The chip size should be 5 mm x 5 mm. We will place the dicing marks. So please do not place anything outside the 5 mm2 chip area.
  • Center the first chip at (0, 0) in a master file and place the rest of your chips in the same master file. The center to center chip spacing should be 5.150 mm in X and/or Y directions in the master file. Make sure there are no name conflicts in cells submitted by your institution. We do not check layouts for name conflicts within an institution.
  • Do not flatten your chips. We rename the master file and its cells to prevent name conflicts between institutions.
  • Please remember that we fabricate and ship several copies of your chips. We guarantee that at least one of the chips meets the process specifications.

1/13/05 — Chip pricing has been revised. Please contact HYPRES for more information.

12/13/04 — Please read the design rules regarding changes implemented in the resistor layer (layer 9: R2).

Starting with the April 23, 2003 release, the 100 A/cm2 (as well as the 30 A/cm2) process will utilize 2 Ohm/sq resistor technology. Please revise all your future layouts accordingly. This change is necessary to accommodate quantum computing chips requiring operation at extremely low temperatures. This change is not yet incorporated into the 1,000 A/cm2 process. The 1,000 A/cm2 process will continue to use the 1 Ohm/sq Mo. Please contact for more information.

Please note that the 100 A/cm2 process will be discontinued after April 2004 release.
The state-of-the-art HYPRES wafer processing technology and micromachining utilize advanced equipment in a controlled clean room with a local class 100 environment. High volume and standard circuit production allow HYPRES customers to take advantage of rapid improvements in both yield and performance.

HYPRES maintains a schedule for its foundry chip fabrication and accepts layouts electronically or using other media according to the specifications in the Nb Process Design Rule document.

Each chip site guarantees delivering of at least one chip that meets all of the specifications in the design rule.