The Niobium Process
HYPRES’ foundry features a complete niobium-based superconducting integrated circuit fabrication line. The niobium process has been in operation since 1983 with proven reliability as demonstrated by circuit operations through 7000 thermal cycles without failure and no changes in device characteristics after five years of shelf life.
State-of-the-Art Wafer Processing
The company’s state-of-the-art wafer processing capability is supported with advanced equipment in Class 100 clean rooms. The high volume capability allows customers to take advantage of rapid improvements in both yield and performance. The company offers customized foundry services in several areas that can be requested through its website, by email, or phone.
1-um Mask Aligner Lithography-based Process (PDF) — For 4 metal layer process only
0.25-um 5x Stepper Lithography-based Process (PDF) — For 4 or more metal layer process
|Cycle Time||8 Weeks|
|Metal Interconnect Levels||4|
|Minimum Feature Size||1.0 micrometer|
|Substrate Size||150 mm|
|Current Density (Fab Specified)||30 A/cm2, 100 A/cm2, 1kA/cm2, 4.5 kA/cm2|
|Current Density Tolerance||+/- 15% run-to-run, +/- 5% on-chip|
|Resistor Tolerance||+/- 15% run-to-run, +/- 5% on-chip|
|Design Media Format||GDS II|
Process Layer Description
|MO||Niobium Ground Plane|
|IO||Silicon Dioxide Insulator|
|I1B||Silicon Dioxide Insulator|
|I2||Silicon Dioxide Insulator|
Using design tools available from HYPRES, the customer can perform circuit design, simulation and layout. The layout is sent to HYPRES in GDS II format for mask preparation.
Wafers are tested for conformance to PCM specifications and visually inspected for quality assurance. Optionally, HYPRES will test device performance. High speed testing is also available. HYPRES has the facilities, resources and expertise to participate in any development phase and can accommodate customers with varying resource and experience levels.
HYPRES has extensive CAD facilities for superconductor digital and mixed-signal integrated circuit (IC) design targeted for its Nb foundry. Since 2009, the company has been increasing its capabilities for designing semiconductor analog and mixed-signal ICs using external foundry (e.g. SiGe). HYPRES primarily uses integrated software packages, CADENCE, Microwave Office and Xic, for layout and simulation of circuits. The team carries out the circuit simulation and layout on several workstations, running LINUX and Windows. HYPRES superconductor IC simulation tools include J-SPICE (a version of SPICE custom modified to apply to superconductor circuits), PSCAN (Custom software systems for the simulation of SFQ circuits), and COWB (automated parameter optimization system). Image: design flow for superconductor and semiconductor ICs. In addition, the company extensively uses MatLAB and Simulink for functional simulations of circuits and systems.
For design of cryopackaging, HYPRES use SolidWorks, AutoCAD, and OrCAD for mechanical designs, and SONNET and Microwave Office for electrical designs.
Proven Foundry Results
|High-Resolution Analog-to-Digital Converter (Phase Modulation-Demodulation) Oversampling modulator clocked at 28 GHz and programmable digital decimation filter: 89 dB SNR at 10 MHz BW, 100 dB SFDR|
|Bandpass Delta-Sigma Analog-to-Digital Converter (various bands, including L, C, X, Ka bands): Up to 32 GHz Clock, 50-65 dB SFDR|
|Flash Analog-to-Digital Converter: 20 dB SNR at 20 GHz BW|
|Ultra-sensitive Analog-to-Digital Converter: 1 microA full-scale range with SQUID front-end|
|Memory RAM: 32-bit, 16 Kb, 100 ps cycle time|
|Shift Register: 19 GHz, 1 Kb|
|Digital Correlator: 40 Gbps 1-bit autocorrelator|
|Time-to-Digital Converter: 33 ps (30 GHz) multi-hit time resolution|
|On-chip Clock Source: 10-1000 GHz SFQ clock, 5-10 fs time jitter|
|Multi-chip Modules: >50 Gbps interchip data transfer|